The present invention relates to a semiconductor fabrication technology, and more particularly, to a method for forming fine patterns of a semiconductor device with a line width of less than 50 nm.
Existing exposure equipment used to fabricate a semiconductor device cannot form a pattern with a line width of less than 60 nm because of its limitation. Meanwhile, a double exposure technique is used to form a pattern with a line width of less than 60 nm. In the double exposure technique, however, a develop inspection critical dimension variation occurs during a secondary exposure process according to overlay values. When assuming that a develop inspection critical dimension variation specification is less than ±5 nm in a 50-nm technology, an overlay control capability must be less than ±5 nm. However, the existing technology cannot achieve it. After a secondary exposure process, a photoresist pattern profile is also poor. To solve this limitation, a spacer is used to reduce a pattern size.
FIGS. 1A to 1D illustrate cross-sectional views showing a method for forming fine patterns of a typical semiconductor device using a spacer to reduce a pattern size.
Referring to FIG. 1A, an etch target layer 11 is formed over a semiconductor substrate (not shown) defining a cell region and a peripheral region. First oxide layers 12 with a width of approximately 80 nm are formed over the etch target layer 11. A gap between the first oxide layers 12 is approximately 100 nm. Nitride spacers 13 with a width of approximately 10 nm are formed on sidewalls of the first oxide layers 12. Referring to FIG. 1B, a second oxide layer 14 is deposited to cover the nitride spacers 13, so that the gap between the nitride spacers 13 is filled.
Referring to FIG. 1C, a chemical mechanical polishing (CMP) process is performed to polish the first and second oxide layers 12 and 14 and the nitride spacers 13, forming etched first oxide layers 12A, etched nitride spacers 13A, and etched second oxide layers 14A. Referring to FIG. 1D, the etched nitride spacers 13A are removed using phosphoric acid. Consequently, a hard mask 15 for patterning the etch target layer 11 to a line width of less than 50 nm is formed. The hard mask 15 is configured with the etched first oxide layers 12A and the etched second oxide layers 14A.
However, the typical method for forming the fine patterns of the semiconductor device may have the following limitation. As illustrated in FIG. 1C, planarization between the cell region and the peripheral region may become non-uniform during the CMP process performed after the deposition of the second oxide layer 14. That is, because the CMP process is performed on the homogeneous oxide layers such as the first and second oxide layers 12 and 14, the control of the polishing process may become difficult so that uniform layers cannot be formed. This limitation is also shown in FIG. 2. As illustrated, after the CMP process, a thickness H1 of the cell region is approximately 1,056 Å and a thickness H2 of the peripheral region is approximately 561 Å. Thus, planarization between the cell region and the peripheral region may become non-uniform.